This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.

chain of inverters, clock-network, CMOS inverter, delay-line, I/O, jitter, power supply induced jitter, power supply noise, tapered buffer, time interval error
IEEE Access
Department of Electronics

Tripathi, J.N. (Jai Narayan), Illikkal, M.S. (Muhammed Suhail), Shrimali, H. (Hitesh), & Achar, R. (2019). A thomas algorithm-based generic approach for modeling of power supply induced jitter in CMOS buffers. IEEE Access, 7, 125240–125252. doi:10.1109/ACCESS.2019.2937922