Using the sub-harmonic injection locking technique, an enhanced differential Digitally Controlled Ring Oscillator (DCRO) with improved phase noise performance is proposed in this paper. All circuit blocks were implemented using digital design flow and designed using a hardware description language. A Frequency Locked Loop-based Process, Voltage and Temperature (PVT) calibrator was utilized to overcome PVT variations. The design was fabricated in 65 nm CMOS technology and its area is 0.017 mm2. The measured phase noise at 1 MHz offset and RMS jitter are −128 dB/Hz and 197fs, respectively. The design was tested in the presence of voltage and temperature variations. The maximum jitter difference percentage is 13.7% at 70 °C and 1.1 V and the phase noise value changes by a maximum of 0.7 dB over the whole range of voltages and temperatures. Furthermore, when the design was tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the DCRO.

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Microelectronics Journal
Department of Electronics

Abou-El-Kheir, N.T. (Nahla T.), Mason, R, Li, M. (Mingze), & Yagoub, M.C.E. (Mustapha C.E.). (2020). A sub-harmonic injection locking clock multiplier with FLL PVT calibrator. Microelectronics Journal, 98. doi:10.1016/j.mejo.2020.104729