Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC-based digitally controlled oscillator (DCO) having a tuning range of 2 GHz, a frequency resolution of 1.2 MHz/LSB, and a low phase noise of -104 dBc/Hz at 1-MHz offset. All PLL digital functions are consolidated in a single, fully synthesized digital signal processing unit operating at 3.5 GHz or 10 $\times $ the reference clock frequency. Limit cycles are minimized without the aid of a time-to-digital converter through substantial reduction of loop latency using a look-ahead digital loop filter. Various design techniques exploiting the advanced 7-nm FinFET technology are discussed, including noise reduction and tank ${Q}$ enhancement. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analog or mixed-mode simulators. Here, the accuracy and computational burden of calculating 1/ ${f}^{\alpha }$ noise is overcome by pre-calculating the DCO and reference phase noise profiles. The results obtained from these simulation techniques show very close agreement with experimental measurements. This 7-nm FinFET PLL occupies a competitive 0.06 mm2 and consumes 40 mW.

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IEEE Journal of Solid-State Circuits
Department of Electronics

Pfaff, D. (Dirk), Abbott, R. (Robert), Wang, X.-J. (Xin-Jie), Moazzeni, S. (Shahaboddin), Mason, R, & Smith, R.R. (Raleigh R.). (2020). A 14-GHz Bang-Bang Digital PLL with Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS. IEEE Journal of Solid-State Circuits, 55(3), 580–591. doi:10.1109/JSSC.2019.2946134