On the conception and analysis of a 12-GHz push-push phase-locked DRO
This paper describes the design and behavior of a 12-GHz push-push dielectric resonator oscillator in a phase-locked environment. This phase-locked dielectric resonator oscillator (PLDRO) differs from conventional designs on many fronts. First, it uses a push-push oscillator for its improved phase noise and reduced fundamental frequency. Second, the phase detection is implemented at a 3-GHz IF as an alternative to detecting at RF using a sampling phase detector (PD). Finally, the push-push PLDRO is tuned via coupled microstrip lines to minimize oscillator loading. These modifications are intended to minimize the risk of PLDRO lock failures by maintaining a constant PD gain via amplifiers operating at P 1dB, and by halving the DRO fundamental frequency using the push-push approach. Experimental results indicate a fundamental suppression of 27 dBc, and single-sideband phase noise densities of -105, -110, and -125 dBc/Hz at 10-kHz, 100-kHz, and 1-MHz offsets, respectively, from a 12-GHz carrier.
|Keywords||Dielectric resonator oscillator (DRO), Loop filter, Multiplier, Oscillator, Phase noise, Phase-locked loop (PLL), Prescaler, Push-push, Sampling phase detector (SPD), Step recovery diode (SRD)|
|Journal||IEEE Transactions on Microwave Theory and Techniques|
Gravel, J.-F. (Jean-François), & Wight, J. S. (2006). On the conception and analysis of a 12-GHz push-push phase-locked DRO. In IEEE Transactions on Microwave Theory and Techniques (Vol. 54, pp. 153–159). doi:10.1109/TMTT.2005.860508