A 4-Gb/s half-rate clock and data recovery circuit (CDR) with a 3-stage voltage-controlled oscillator (VCO), and a novel phase/frequency detector (PFD) is reported in this paper. The VCO produces multiple-phase clocks spaced by one-third of the incoming data symbol period. A novel PFD is employed to compare the multiple-phase clocks with the incoming data and produce the error signals to tune the VCO frequency with the aid of a charge pump and a loop filter. The PFD also produces a signal to enlarge the charge pump current during the frequency acquisition stage so that a fast frequency acquisition can be achieved. This CDR was implemented in CMOS 0.18μm technology and its feasibility was confirmed by post-layout simulations.

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Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
Department of Electronics

Zhuang, J. (Jingcheng), Du, Q. (Qingjin), & Kwasniewski, T. (2005). A 4-GB/S half-rate clock and data recovery circuit with A 3-stage VCO. Presented at the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005.