This paper presents a complete noise analysis of a Σ -based fractional-N phase-locked loop (PLL) based frequency synthesizer. Rigorousanalytical and empirical formulas have been given to modelvarious phase noise sources and spurious components and topredict their impact on the overall synthesizer noiseperformance. These formulas have been applied to an integratedmultiband WLAN frequency synthesizer RFIC to demonstrate noiseminimization through judicious choice of loop parameters.Finally, predicted and measured phase jitter showed goodagreement. For an LO frequency of 4.3 GHz, predicted and measuredphase noise was 0.50°rms and 0.535°rms, respectively.

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Journal Eurasip Journal on Wireless Communications and Networking
Rogers, J, Dai, F.F. (Foster F.), Plett, C, & Cavin, M.S. (Mark S.). (2006). Design and characterization of a 5.2 GHz/2.4 GHz Σ fractional-N frequency synthesizer for low-phase noise performance. Eurasip Journal on Wireless Communications and Networking, 2006, 1–11. doi:10.1155/WCN/2006/48489