An outlier detection technique based on joint estimation of model parameters and outlier effects in time series is implemented in FPGA-based configurable real-time outlier detection hardware. The hardware models time series data with an autoregressive-moving-average (ARMA) process and identifies the outliers based on test statistics using unbiased parameters. A configurable hardware implementation was written in Verilog, simulated to verify its correctness, and synthesized on an Altera FPGA device from the Stratix V family. The design is configurable by adjusting the number of iterations for the optimization process, the number of samples in the time series data, and the critical value. A reported configuration of this design has a total power dissipation of 1.14W, while processing 35 million data points per second, giving an energy usage of 32 nJ per processed data point. The implemented hardware is capable of detecting multiple additive outliers in time series data with a detection accuracy of 99% and has a type I error rate of 1.05%. Compared to a general purpose CPU running a software implementation of the outlier detection algorithm, the FPGA implementation reduces the power consumption by 89% at similar rates of data throughput.
63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020
Department of Electronics

MacEachern, L, & Vazhbakht, G. (Ghazaleh). (2020). Configurable FPGA-Based Outlier Detection for Time Series Data. In Midwest Symposium on Circuits and Systems (pp. 142–145). doi:10.1109/MWSCAS48704.2020.9184548