A pipelined two post-tap half-rate decision feedback equalizer (HRDFE) is proposed. The circuit is composed of equalizing circuit and sampling circuit working at half rate clock, with cross-coupling output of interleaving sampler feedback to the input. A behavioral model of the HRDFE is built in MATLAB to prove the feasibility of the circuit. The design is verified by using 0.18μm CMOS process in SPECTRE. Simulation results show eye opening increases at speed up to 6.25Gb/s with data transmitted over a 34" FR4 backplane. The total power consumption is 8.91mW with a 1.8V supply.

Additional Metadata
Persistent URL dx.doi.org/10.1109/NEWCAS.2005.1496689
Conference 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
Citation
Chen, J. (Jing), & Kwasniewski, T. (2005). A 6.25Gb/s pipelined half-rate decision feedback equalizer for high speed backplane data communications. Presented at the 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005. doi:10.1109/NEWCAS.2005.1496689