This paper presents an oversampling Data Recovery (DR) architecture using Verilog-A that employs a novel Multiple-Rotating-Clock-Phase (MRCP) concept for its operation. The MRCP-DR architecture is a variant of the eye-tracking DR architecture [7]. Multiple rotating clock phases, supplied by a Delay-Locked Loop (DLL), establish a window for detecting data edges. As a result, the window width becomes robust against Process, Voltage and Temperature (PVT) variations. The MRCP architecture is tolerant of jitter on the local, blind, free-running oscillator that operates at approximately the incoming data frequency. Behavioral blocks are described and functional simulations are presented using the Verilog-A/Spectre/Cadence platform. The Verilog-A test benches allow the designer to perform system-level what-if analyses and make area, power and performance estimates.

Additional Metadata
Keywords Behavioral Modeling, Data Recovery, Jitter Tolerance, MRCP, Tracking, Verilog-A
Persistent URL dx.doi.org/10.1109/BMAS.2005.1518197
Conference BMAS 2005 - 2005 IEEE International Behavioral Modeling and Simulation Workshop
Citation
Ahmed, S.I., & Kwasniewski, T. (2005). A multiple-rotating-clock-phase architecture for digital data recovery circuits using Verilog-A. Presented at the BMAS 2005 - 2005 IEEE International Behavioral Modeling and Simulation Workshop. doi:10.1109/BMAS.2005.1518197