Recent trends in the commercial use of fractional-N frequency synthesis can be attributed to the characteristic of independent loop bandwidth-channel spacing that results in low phase noise and relaxes the Phase-Locked Loop (PLL) design constraints. This paper reviews several techniques used to implement fractional-N frequency synthesizers and discusses the advantages and disadvantages. It also addresses design options and associated trade-offs.

Additional Metadata
Persistent URL dx.doi.org/10.1109/IWSOC.2005.91
Conference Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005
Citation
Zarkeshvari, F. (Farhad), Noel, P. (Peter), & Kwasniewski, T. (2005). PLL-based fractional-N frequency synthesizers. Presented at the Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005. doi:10.1109/IWSOC.2005.91