Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing, A receiver implemented in 0.18-μm CMOS technology demonstrates 6,25Gb/s and 8Gb/s operation over a 34" FR4 backplane.

Additional Metadata
Persistent URL dx.doi.org/10.1109/IWSOC.2005.48
Conference Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005
Citation
Li, M. (Miao), Noel, P. (Peter), Kwasniewski, T, & Wang, S. (Shoujun). (2005). Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications. Presented at the Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005. doi:10.1109/IWSOC.2005.48