2005-12-01
On ΔΣ fractional-n frequency synthesizers
Publication
Publication
Presented at the
ISSCS 2005: International Symposium on Signals, Circuits and Systems (July 2005)
ΔΣ fractional-N frequency synthesis achieves low phase noise performance while relaxing the Phase-Locked Loop (PLL) design constraints and reduces the desired channel spacing. This paper reviews the recent advanced techniques on the implementation of fractional-N frequency synthesizers and discusses their advantages and disadvantages. It also addresses the design options and the associated trade-offs.
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| dx.doi.org/10.1109/ISSCS.2005.1511289 | |
| ISSCS 2005: International Symposium on Signals, Circuits and Systems | |
| Organisation | Department of Electronics |
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Zarkeshvari, F. (Farhad), Noel, P. (Peter), & Kwasniewski, T. (2005). On ΔΣ fractional-n frequency synthesizers. Presented at the ISSCS 2005: International Symposium on Signals, Circuits and Systems. doi:10.1109/ISSCS.2005.1511289
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