ΔΣ fractional-N frequency synthesis achieves low phase noise performance while relaxing the Phase-Locked Loop (PLL) design constraints and reduces the desired channel spacing. This paper reviews the recent advanced techniques on the implementation of fractional-N frequency synthesizers and discusses their advantages and disadvantages. It also addresses the design options and the associated trade-offs.

Additional Metadata
Persistent URL dx.doi.org/10.1109/ISSCS.2005.1511289
Conference ISSCS 2005: International Symposium on Signals, Circuits and Systems
Citation
Zarkeshvari, F. (Farhad), Noel, P. (Peter), & Kwasniewski, T. (2005). On ΔΣ fractional-n frequency synthesizers. Presented at the ISSCS 2005: International Symposium on Signals, Circuits and Systems. doi:10.1109/ISSCS.2005.1511289