2005-12-01
A 1.2V CMOS multiplier for 10 Gbit/s equalization
Publication
Publication
Presented at the
ESSCIRC 2005: 31st European Solid-State Circuits Conference (September 2005)
| Additional Metadata | |
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| Persistent URL | dx.doi.org/10.1109/ESSCIR.2005.1541639 |
| Conference | ESSCIRC 2005: 31st European Solid-State Circuits Conference |
| Citation |
Abbott, J. (Justin), Plett, C, & Rogers, J. (2005). A 1.2V CMOS multiplier for 10 Gbit/s equalization. Presented at the ESSCIRC 2005: 31st European Solid-State Circuits Conference. doi:10.1109/ESSCIR.2005.1541639
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