A 1.2V CMOS multiplier for 10 Gbit/s equalization

2005-12-01

Presented at the ESSCIRC 2005: 31st European Solid-State Circuits Conference (September 2005)

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Persistent URL	dx.doi.org/10.1109/ESSCIR.2005.1541639
Conference	ESSCIRC 2005: 31st European Solid-State Circuits Conference
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Abbott, J. (Justin), Plett, C, & Rogers, J. (2005). A 1.2V CMOS multiplier for 10 Gbit/s equalization. Presented at the ESSCIRC 2005: 31st European Solid-State Circuits Conference. doi:10.1109/ESSCIR.2005.1541639

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