A high-speed analog min-sum iterative decoder
Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Proposed circuits are devised based on current mirrors. Therefore, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed modules was verified by implementing an analog MS decoder for a (32,8,10) regular LDPC code in 0.18-μm CMOS technology. In low signal to noise ratios when the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional MS decoder, and is close to the performance predicted by the earlier work on the dynamics of the continuous-time analog decoding by Hemati and Banihashemi, ISIT2004. At a throughput of 24Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10-3 is about 0.3dB. To the best of our knowledge, this decoder has the highest throughput and the lowest power/speed ratio among the reported analog CMOS iterative decoders.
|Conference||2005 IEEE International Symposium on Information Theory, ISIT 05|
Hemati, S. (Saied), Banihashemi, A, & Plett, C. (2005). A high-speed analog min-sum iterative decoder. Presented at the 2005 IEEE International Symposium on Information Theory, ISIT 05. doi:10.1109/ISIT.2005.1523649