Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-μm CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10 -3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one.

Additional Metadata
Keywords Analog iterative decoder, Belief propagation, Current-mode circuits, Low-density parity-check (LDFC) codes, Min-sum decoding, Turbo codes
Persistent URL dx.doi.org/10.1109/JSSC.2006.883329
Journal IEEE Journal of Solid-State Circuits
Citation
Hemati, S. (Saied), Banihashemi, A, & Plett, C. (2006). A 0.18-μm CMOS analog min-sum iterative decoder for a (32,8) low-density parity-check (LDPC) code. In IEEE Journal of Solid-State Circuits (Vol. 41, pp. 2531–2540). doi:10.1109/JSSC.2006.883329