Phase-Locked Loop (PLL) based Clock and Data Recovery (CDR) circuits use a 2x-oversampling (2XO) of the incoming Non-Return to Zero (NRZ) data stream to recover the data. As an extension of the idea, 3x-oversampling (3XO) CDR circuits provide improved performance in the presence of total asymmetric jitter. This paper presents an overview of the oversampling CDR circuits with an emphasis on digital architectures. These include, but are not limited to, the 3XO jitter-tolerant variable-interval 3XO architecture, the 3XO eye-tracking architecture, and the blind oversampling architecture. We propose a modified architecture that utilizes multiple rotating phases to improve the performance of the 3XO eye-tracking architecture.

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Keywords CDR, DR, Jitter tolerance, Oversampling, PLL
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Conference Canadian Conference on Electrical and Computer Engineering 2005
Ahmed, S.I., & Kwasniewski, T. (2005). Overview of oversampling clock and data recovery circuits. Presented at the Canadian Conference on Electrical and Computer Engineering 2005. doi:10.1109/CCECE.2005.1557348