A clock and data recovery circuit is an important building block in data communication systems and the phase detector (PD) is one of the critical parts of a CDR. A bang-bang phase detector is suitable for low-power high-bit-rate operation, but a separate frequency detector (FD) has to be used for frequency acquisition, which results in some problems such as frequency drift, sudden phase jump due to the disaccord of the PD and FD. To solve these problems, this paper proposes a novel phase/frequency detector (PFD) with an extended operating range and a multiple-level output for half-rate CDR applications. Because of its multiple-level output, the CDR can achieve lower output clock jitter than a conventional binary PD. The proposed PFD has an operating speed comparable to conventional bang-bang PDs and can also be used in full-rate CDRs with minor modification. The simulation of a half-rate CDR model employing this type of PFD confirms the feasibility of the proposed PFD.

Additional Metadata
Keywords Clock data recovery, Frequency acquisition, Frequency detector, Phase detector
Persistent URL dx.doi.org/10.1109/CCECE.2005.1557056
Conference Canadian Conference on Electrical and Computer Engineering 2005
Jingcheng, Z. (Zhuang), & Kwasniewski, T. (2005). A multi-level phase/frequency detector for clock and data recovery applications. Presented at the Canadian Conference on Electrical and Computer Engineering 2005. doi:10.1109/CCECE.2005.1557056