Phase noise improvement of deep submicron low-voltage VCO
A low-voltage wideband 3.0-5.0 GHz complementary VCO was designed and fabricated in an 0.13 μm SOI CMOS process . Non-minimum gate length was used for NMOS to improve the phase noise by exploiting waveform symmetry, maximizing output swing and reducing transistor flicker noise without any penalty to VCO performance. A phase noise improvement of up to 8 dB was observed experimentally. At 1 V VDDand 3.0 GHz, the phase noise is - 122.5 dBc/Hz at 1MHz offset, and the power dissipation is 2.5mW.
|28th European Solid-State Circuits Conference, ESSCIRC 2002|
|Organisation||Department of Electronics|
Fong, N. (Neric), Plett, C, Tarr, G. (Garry), Plouchart, J.-O. (Jean-Olivier), Liu, D. (Duixian), Zamdmer, N. (Noah), & Wagner, L. (Lawrence). (2002). Phase noise improvement of deep submicron low-voltage VCO. Presented at the 28th European Solid-State Circuits Conference, ESSCIRC 2002.