2005-12-01
Behavioral test benches for digital clock and data recovery circuits using Verilog-A
Publication
Publication
Presented at the
IEEE 2005 Custom Integrated Circuits Conference (September 2005)
This paper presents the behavioral implementation of jitter tolerance test benches for digital clock and data recovery circuits using Verilog-A. First, we encode a variable-length Pseudo-Random Bit Sequence (PRBS) generator. Such circuits are widely used to generate test data for a variety of circuits and systems. Using this PRBS generator, we set up a test bench for the evaluation of jitter tolerance. A novel simulation methodology is described that modulates the amplitude and frequency of the jitter sinusoid iteratively to find the jitter tolerance. We conclude with a comparison of jitter tolerance simulation results, computed using various PRBS lengths, for the data recovery circuit under test.
| Additional Metadata | |
|---|---|
| Behavioral, Data recovery, Jitter tolerance, PRBS, SoC, Verilog-A | |
| dx.doi.org/10.1109/CICC.2005.1568664 | |
| IEEE 2005 Custom Integrated Circuits Conference | |
| Organisation | Department of Electronics |
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Ahmed, S.I., Orthner, K. (Kent), & Kwasniewski, T. (2005). Behavioral test benches for digital clock and data recovery circuits using Verilog-A. Presented at the IEEE 2005 Custom Integrated Circuits Conference. doi:10.1109/CICC.2005.1568664
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