An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code

2005-12-01

Presented at the IEEE 2005 Custom Integrated Circuits Conference (September 2005)

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Persistent URL	dx.doi.org/10.1109/CICC.2005.1568652
Conference	IEEE 2005 Custom Integrated Circuits Conference
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Hemati, S. (Saied), Banihashemi, A, & Plett, C. (2005). An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code. Presented at the IEEE 2005 Custom Integrated Circuits Conference. doi:10.1109/CICC.2005.1568652

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