With the ever increasing signal speeds, signal integrity issues of high-speed VLSI designs are presenting increasingly difficult challenges for state-of-the-art modeling and simulation tools. Consequently, characterization and passive macromodeling of high-speed modules such as interconnects, vias, and packages based on tabulated data are becoming important. This paper presents a fast algorithm for passivity verification and enforcement of large order macromodels of scattering parameter based multiport subnetworks. Numerous examples tested on this algorithm demonstrate a significant speed-up compared to the existing algorithms in the literature.

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Department of Electronics

Saraswat, D. (Dharmendra), Achar, R, & Nakhla, M.S. (2007). Fast passivity verification and enforcement via reciprocal systems for interconnects with large order macromodels. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(1), 48–59. doi:10.1109/TVLSI.2007.891085