2003
A delay-locked frequency synthesizer with low phase noise performance
Publication
Publication
Presented at the
IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (December 2003), Tsimshatsui, Kowloon
This paper presents a delay-locked frequency synthesizer implemented in 0.18 μm CMOS technology. Symmetrical structures were employed in the circuit to reduce the inter-period jitter and phase noise. With the reference signal from an RF generator, the measured phase noise performance is of -105.5dBc/Hz at 10kHz offset with the carrier frequency of 2.07GHz.
| Additional Metadata | |
|---|---|
| doi.org/10.1109/EDSSC.2003.1283573 | |
| IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 | |
| Organisation | Department of Electronics |
|
Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2003). A delay-locked frequency synthesizer with low phase noise performance. Presented at the IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. doi:10.1109/EDSSC.2003.1283573
|
|