2006-12-01
A 0.18-μm CMOS clock and data recovery circuit with extended operation range
Publication
Publication
Presented at the
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems (May 2006)
A clock and data recovery architecture for highspeed communication systems is proposed. Based on early-late method, the bang-bang phase and frequency detector works in two modes: half-rate mode and quarter-rate mode, thus a large applicable data rate range is available. Simulated in a 0.18-μm CMOS technology, the circuit exhibits a peak-to-peak jitter of 48ps in the recovered quarter-rate clock with PRBS length of 215-1 at 6.25-Gb/s. The data is recovered and demultiplexed inherently. In quarter-rate mode, the power dissipation is 8OmW from a 1.8V supply.
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| Conference | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems |
| Citation |
Li, M. (Miao), Huang, W. (Wenjie), Kwasniewski, T, & Wang, S. (Shoujun). (2006). A 0.18-μm CMOS clock and data recovery circuit with extended operation range. Presented at the ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems.
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