A 0.13 μm CMOS delay cell for 40 Gb/s FFE equalization

2006-12-01

Presented at the ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems (May 2006)

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Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Lovitt, T. (Travis), Plett, C, & Rogers, J. (2006). A 0.13 μm CMOS delay cell for 40 Gb/s FFE equalization. Presented at the ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems.

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