Quantization noise reduction using multiphase PLLs
A 120MHz fractional-N frequency synthesizer was implemented in a standard 0.18μm CMOS process with an on-chip multiphase voltage-controlled oscillator (VCO). The proposed architecture uses multiphase outputs of the VCO to decrease quantization noise from the Sigma-Delta (ΣΔ) modulator. Results show the decrease in quantization noise from the 4 th order ΣΔ is 6dB for every two fold increase in the number of phases. The VCO phase noise was measured to be -104dBc/Hz at 200kHz offset. The loop bandwidth can be increased to 700kHz and still maintain in-band quantization noise below -100dBc/Hz. The power consumption of the synthesizer is 5.4mW with a 1.8V supply and it occupies an active area of 750μm × 550μm. The intended application is subharmonic injection higher frequency VCO and as a clock generator in a subsampling analog-to-digital converter (ADC).
|Conference||ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems|
Miletic, I. (Igor), & Mason, R. (2006). Quantization noise reduction using multiphase PLLs. Presented at the ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems.