A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction

Du, Q. (Qingjin), Zhuang, J. (Jingcheng) and T. Kwasniewski (Tad)

2006-01-01

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , Volume 53 - Issue 11 p. 1205- 1209

Additional Metadata
Keywords	Delay-locked loop (DLL), Frequency multiplier, In-lock error, Phase noise, Phase-locked loop (PLL), Spurious power level
Persistent URL	dx.doi.org/10.1109/TCSII.2006.883103
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2006). A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 53(11), 1205–1209. doi:10.1109/TCSII.2006.883103

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