2006
A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction
Publication
Publication
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , Volume 53 - Issue 11 p. 1205- 1209
Additional Metadata | |
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Delay-locked loop (DLL), Frequency multiplier, In-lock error, Phase noise, Phase-locked loop (PLL), Spurious power level | |
dx.doi.org/10.1109/TCSII.2006.883103 | |
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | |
Organisation | Department of Electronics |
Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2006). A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 53(11), 1205–1209. doi:10.1109/TCSII.2006.883103
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