Additional Metadata
Keywords Delay-locked loop (DLL), Frequency multiplier, In-lock error, Phase noise, Phase-locked loop (PLL), Spurious power level
Persistent URL dx.doi.org/10.1109/TCSII.2006.883103
Journal IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Citation
Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2006). A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 53(11), 1205–1209. doi:10.1109/TCSII.2006.883103