This paper discusses the design of all-silicon pulse-compression nonlinear transmission lines (NLTLs), using a standard 0.18-μm CMOS process. Two different types of varactors based on NMOS transistors are investigated One type is used in a single-edge, the other in a double-edge pulse-sharpener NLTL. To reduce the loss caused by conductive silicon substrate, a slow-wave transmission line technique is used. A measured S21 loss of only 0.25dB/mm at 40GHz is achieved. Both NMOS varactor and slow-wave coplanar-waveguide (CPW) transmission-line components for use in NLTL designs were fabricated and on-chip measurements were made. Transient simulations based on the measurements show a leading edge rise time reduction of 75% for single-edge, and 60% for double-edge pulse sharpening.

, , , , ,
2007 IEEE MTT-S International Microwave Symposium, IMS 2007
Department of Electronics

Li, M. (Ming), Amaya, R, Duchamp, J.-M. (Jean-Marc), Ferrari, P. (Philippe), Harrison, R.G. (Robert G.), & Tarr, N.G. (2007). Low-loss low-cost all-silicon CMOS NLTLs for pulse compression. Presented at the 2007 IEEE MTT-S International Microwave Symposium, IMS 2007. doi:10.1109/MWSYM.2007.380485