This paper describes a new algorithm to obtain reduced-order models for large networks with delay elements. The proposed algorithm can be used in situations where delay extraction-based modeling approaches have been used to model portions of interconnects with low losses, while other portions could be modeled with large networks of lumped components. It is shown that the reduced-order model is passive by construction.

Additional Metadata
Keywords High-speed interconnect, Macromodeling, Model-order reduction delay system, Passivity
Persistent URL dx.doi.org/10.1109/TADVP.2007.906240
Journal IEEE Transactions on Advanced Packaging
Citation
Tseng, W. (Wenliang), Chen, C. (Changzhong), Gad, E. (Emad), Nakhla, M.S, & Achar, R. (2007). Passive order reduction for RLC circuits with delay elements. IEEE Transactions on Advanced Packaging, 30(4), 830–840. doi:10.1109/TADVP.2007.906240