An anti-harmonic locking, DLL frequency multiplier with low phase noise and reduced spur
This paper presents a new programmable delay-locked loop based frequency multiplier with a period error compensation loop (PECL) designed to reduce the output spurious power level. The low bandwidth auxiliary PECL compensates the output period error caused by the in-lock errors from various noise sources. By employing a novel switching control scheme, the circuit is capable of locking to frequencies either above or below the start up frequency without initialization. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 900 MHz to 2.9 GHz. The circuit is implemented in TSMC 0.18μm CMOS technology and measured with the reference signal from an RF signal generator. A 23 dB spur reduction from -23dB to -46.5dB at 1.216GHz is observed from the measurement results. The measured cycle-to-cycle timing jitter at 2.16GHz is 1.6ps (rms) and 12.9 ps (pk-pk), and the measured phase noise is -110 dBc/Hz at 100 kHz offset with a power consumption of 19.8 mW at a 1.8 V supply.
|Conference||IEEE 2006 Custom Integrated Circuits Conference, CICC 2006|
Du, Q.J., Zhuang, J.C., & Kwasniewski, T. (2006). An anti-harmonic locking, DLL frequency multiplier with low phase noise and reduced spur. Presented at the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006. doi:10.1109/CICC.2006.320973