A low phase noise DLL clock generator with a programmable dynamic frequency divider
A delay-locked loop based clock generator with the multiplication ratios from 13 to 20 using a programmable dynamic frequency divider is presented in this paper. Compared with the conventional dividers, a dynamic frequency divider achieves both low transistor count and low power consumption. This design employs re-circulating DLL structure to remove the phase noise accumulated within each reference period, and avoid the effect of the mismatch among delay stages to improve the output jitter performance. Implemented in 0.18 urn CMOS technology, this design operates up to 2.9 GHz. With a reference signal from an RF signal generator, the measured phase noise for the carrier frequency of 2.795 GHz is-110 dBc/Hz at 100 kHz offset, and the RMS timing jit ter at 2 GHz is 3.68 pS. The circuit consumes approximately19 m W at 2 GHz output and occupies an area of less than 0.06 mm 2.
|Clock generator, DLL, PLL, Timing jitter|
|2006 Canadian Conference on Electrical and Computer Engineering, CCECE'06|
|Organisation||Department of Electronics|
Qingjin, D. (Du), Jingcheng, Z. (Zhuang), & Kwasniewski, T. (2007). A low phase noise DLL clock generator with a programmable dynamic frequency divider. Presented at the 2006 Canadian Conference on Electrical and Computer Engineering, CCECE'06. doi:10.1109/CCECE.2006.277703