A 4GHz low complexity ADPLL-based frequency synthesizer in 90nm CMOS

Jingcheng, Z. (Zhuang), Qingjin, D. (Du) and T. Kwasniewski (Tad)

2008-02-27

Presented at the 2007 IEEE Custom Integrated Circuits Conference, CICC (September 2007)

Additional Metadata
Persistent URL	doi.org/10.1109/CICC.2007.4405790
Conference	2007 IEEE Custom Integrated Circuits Conference, CICC
Organisation	Department of Electronics
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Jingcheng, Z. (Zhuang), Qingjin, D. (Du), & Kwasniewski, T. (2008). A 4GHz low complexity ADPLL-based frequency synthesizer in 90nm CMOS. Presented at the 2007 IEEE Custom Integrated Circuits Conference, CICC. doi:10.1109/CICC.2007.4405790

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