Design of high gain fully-integrated distributed amplifiers in 0.35 μm CMOS
A 3.3V single-supply fully-integrated distributed amplifier was implemented in a standard 0.35 μm CMOS process up to 20 dB of gain and a bandwidth of 5.5 GHz. This is the highest reported gain for a CMOS distributed amplifier. Octagonal inductors with no ground shield were implemented in top available metal. Design guidelines for optimizing amplifier gain are presented. Chip dimensions are 0.95 × 1.8 mm2 and power dissipation is 86.7 mW, drawn from a 3.3V supply.
|Conference||29th European Solid-State Circuits Conference, ESSCIRC 2003|
Amaya, R, & Plett, C. (2003). Design of high gain fully-integrated distributed amplifiers in 0.35 μm CMOS. Presented at the 29th European Solid-State Circuits Conference, ESSCIRC 2003. doi:10.1109/ESSCIRC.2003.1257093