In a MIMO communication system, K-best decoding algorithm achieves near optimal performance with reduced complexity. Simulation results show that a reconfigurable MIMO detector can improve system performance over a wide range of operating conditions. In this paper we present a low complexity reconfigurable architecture for implementation of K-best algorithm. Implementation results using FPGA technology demonstrate a throughput of 240Mbps.

Additional Metadata
Keywords FPGA, K-best, MIMO, Reconfigurable hardware
Persistent URL dx.doi.org/10.1109/ISPACS.2007.4445895
Conference 2007 International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2007
Citation
Shariat-Yazdi, R. (Ramin), & Kwasniewski, T. (2008). Reconfigurable K-best MIMO detector architecture and FPGA implementation. Presented at the 2007 International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2007. doi:10.1109/ISPACS.2007.4445895