A timing jitter reduction technique in a cyclic injection clock multiplier for data communication system
This paper presents a jitter reduction technique utilized in a cyclic injection DLL clock generator to improve the output timing jitter performance for data communication systems. An auxiliary loop with a period error detector finely tunes the VCDL delay value to minimize the period variations. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 0.9 GHz to 2.9 GHz. The circuit is implemented in 0.18μm CMOS technology and a significant cycle-to-cycle timing jitter reduction from 21 ps to 2.5 ps at 2.9GHz is obtained from the measured results when the jitter reduction technique is enabled. The measured phase noise is -119.6dBc/Hz at 100 kHz offset with the carrier frequency of 2.795 GHz.
|Conference||2006 IEEE International Systems-on-Chip Conference, SOC|
Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2007). A timing jitter reduction technique in a cyclic injection clock multiplier for data communication system. Presented at the 2006 IEEE International Systems-on-Chip Conference, SOC. doi:10.1109/SOCC.2006.283864