Parallel simulation of high-speed interconnects using delay extraction and transverse partitioning
The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. In this paper, a transverse partitioning algorithm is presented for transient analysis of large multiconductor transmission line circuits. The new method uses a passive delay extraction-based macromodelling algorithm which makes the method suitable for both long and short lines. The computational cost of the proposed method grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity.
|IEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP|
|Organisation||Department of Electronics|
Nakhla, N. (Natalie), Nakhla, M.S, Achar, R, & Ruehli, A. (Albert). (2007). Parallel simulation of high-speed interconnects using delay extraction and transverse partitioning. In IEEE Topical Meeting on Electrical Performance of Electronic Packaging (pp. 237–240). doi:10.1109/EPEP.2007.4387170