This paper emphasizes on the design and analysis of Current Mode Logic latches and their application in a frequency prescaler. Operation of a conventional CML latch is analyzed and a clock feedback structure is proposed for increased stability with reduced delay parameters. A low power design technique is presented for Current Mode Logic frequency prescalers, which allows the Master and Slave latches to be merged together so that they use a single current source. This significantly reduces the power consumption and area and also offers lower terminal capacitances resulting in faster circuit operation.

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doi.org/10.1109/CCECE.2004.1347586
Canadian Conference on Electrical and Computer Engineering; Technology Driving Innovation, 2004
Department of Electronics

Usama, M. (Muhammad), & Kwasniewski, T. (2004). New CML latch structure for high speed prescaler design. Presented at the Canadian Conference on Electrical and Computer Engineering; Technology Driving Innovation, 2004. doi:10.1109/CCECE.2004.1347586