Design and implementation of a multi-carrier demodulator
This paper presents a design and implementation of a multi-carrier demodulator (MCD) circuit. The circuit is designed to handle eight channels at Tl data rates. The design, implementation, and simulations are based on Altera's APEX20K1500 SRAM PLD devices. The MCD circuit design is validated by comparing the performance with functional models developed with SystemView and its communications library. Simulation results for the Tl channel rate MCD design are presented. Circuit test and verification results at both maximum throughput and Tl data rates under typical operating conditions are presented.
|Multi-carrier Demodulator, Polyphase-FFT, System on a Chip|
|Organisation||Department of Electronics|
Ho, H., Szwarc, V., Loo, C., & Kwasniewski, T. (2002). Design and implementation of a multi-carrier demodulator.