2008-08-22
A 42-Gb/s decision circuit in 0.13μm CMOS
Publication
Publication
Presented at the
6th Annual Communication Networks and Services Research Conference, CNSR 2008 (May 2008)
In this paper, a decision circuit based on 0.13 μm CMOS is presented. It is designed for 40-Gb/s optical communication systems. This decision circuit achieved by master-slave flip-flops (MS-FFs) with opposite clock can operate at a bit rate of 40-Gb/s and beyond. Current-mode logic (CML) is adopted due to the higher speed compared to static CMOS and the robustness against common-mode disturbances. A 3-stage output buffer is employed to drive the external 50 Ω loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The decision circuit uses a single 1.2V supply and consumes a total current of 33mA. And the chip area is only 0.63mm2 with bonding pads.
| Additional Metadata | |
|---|---|
| Persistent URL | dx.doi.org/10.1109/CNSR.2008.15 |
| Conference | 6th Annual Communication Networks and Services Research Conference, CNSR 2008 |
| Citation |
Liang, B. (Bangli), Kwasniewski, T, & Chen, D. (Dianyong). (2008). A 42-Gb/s decision circuit in 0.13μm CMOS. Presented at the 6th Annual Communication Networks and Services Research Conference, CNSR 2008. doi:10.1109/CNSR.2008.15
|