Decision-feedback equalization (DFE) is explored to reduce inter-symbol interference (ISI) and crosstalks in highspeed backplane applications. In the design of clock and data recovery (CDR) circuit, embedding DFE within phase and frequency detector (PFD) enhances to recover data inherently from distorted input signals and facilitates to provide DFE with recovered clock. With PRBS15 data signaling at 5-Gb/s over 34" FR4 backplane, SPECTRE simulation in 0.18-μm CMOS process has shown the design feasibility.

Additional Metadata
Persistent URL dx.doi.org/10.1109/APCCAS.2006.342266
Conference APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Citation
Li, M. (Miao), Kwasniewski, T, & Wang, S. (Shoujun). (2006). A 0.18-μm CMOS receiver with decision-feedback equalization for backplane applications. Presented at the APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. doi:10.1109/APCCAS.2006.342266