Clock and Data Recovery (CDR) Circuits are being increasingly marketed as Intellectual Property (IP) blocks for complex System-on-Chip (SoC) and Network-on-Chip (NoC) products. As part of the mixed-signal design flow, an early estimation of system-level performance requires efficient simulation techniques and models to establish design requirements. In this paper we present some of the challenges associated with and efficient methods to estimate the jitter tolerance of an all-digital data recovery circuit. The key insight is that since it is the maximum slope of the phase-modulating sinusoid that causes transient bit errors, an arbitrary waveform with the same maximum slope can be used for a shorter simulation study. We also present known limitations associated with the general usage of this newly proposed method.

Additional Metadata
Keywords Behavioral, BERT, Data recovery, Jitter tolerance, PRBS, SoC, Verilog-A
Persistent URL dx.doi.org/10.1109/MWSCAS.2007.4488745
Conference 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
Citation
Ahmed, S.I., & Kwasniewski, T. (2007). Efficient simulation of jitter tolerance for all-digital data recovery circuits. Presented at the 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference. doi:10.1109/MWSCAS.2007.4488745