A 0.18-μm CMOS clock and data recovery circuit with reference-less dual loops
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-to-peak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of -93.5 dBc/Hz at 1-MHz offset. The core circuit consumes 40 mW at 1.8-V supply and occupies an area of 0.3 mm2.
|Conference||2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008|
Li, M. (Miao), Kwasniewski, T, & Wang, S. (Shoujun). (2008). A 0.18-μm CMOS clock and data recovery circuit with reference-less dual loops. Presented at the 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. doi:10.1109/ISCAS.2008.4541928