An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. Implemented in a CMOS 0.13μm technology, the PFD and the CP dissipate 3.73mW and a 460μW DC power from a 1V supply, respectively. The occupied chip area of the PFD is 68×24μm2, and that of the CP is 68×23μm 2. With a spurious free dynamic range of a 80dBc, a phase noise of a -95dBc/Hz at 100kHz offset, a low power and a small layout area the presented PFD and CP are suitable for integrated radio applications operating between 2.4GHz and 10GHz, such as 802.11 and WiMax for example.

Additional Metadata
Keywords Charge pump, CP, Frequency synthesizer, Loop filter, PFD, Phase frequency detector, PLL
Persistent URL dx.doi.org/10.1109/ISCAS.2008.4541722
Conference 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Citation
Milicevic, S. (Sinisa), & MacEachern, L. (2008). A phase-frequency detector and a charge pump design for PLL applications. Presented at the 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. doi:10.1109/ISCAS.2008.4541722