Pre-emphasis is often employed at the transmitter side to counteract the inter symbol interface (ISI) in high-speed data communications. Traditional pre-emphasis drivers, implemented in CML, use one pair of CMOS transistors as the output stage. To design a pre-emphasis for different channels or the same channel using different type of equalizer requires a wide range of current for the same tap. The challenge for traditional circuits is how to choose the sizes for these transistors. To meet this challenge, this paper presents a lower 6-tap pre-emphasis with several pairs of transistors at output stage to solve this issue. The simulation shows the eye diagram for the same channel improved vertical 8% and horizontal 5%. The pre-emphasis consumes only 57.7mW with a total of 6 tabs.

Additional Metadata
Persistent URL dx.doi.org/10.1109/BSC.2008.4563213
Conference 24th Biennial Symposium on Communications, BSC 2008
Citation
Cheng, D. (Dezhong), Liang, B. (Bangli), Chen, D. (Dianyong), & Kwasniewski, T. (2008). A reduced power 6-tap pre-emphasis for 10GB/S backplane communications. Presented at the 24th Biennial Symposium on Communications, BSC 2008. doi:10.1109/BSC.2008.4563213