This paper presents a reconfigurable systolic array design suitable for multi-carrier wireless applications. The systolic array architecture includes coarse grained processing elements and interconnection switches. The systolic array can be configured as a Polyphase-FIR filter, DFT, Polyphase-DFT and IDFT-Polyphase function. A representative reconfigurable circuit has been designed and implemented on an FPGA for operation in the following modes: 32-point DFT; 8-channel Polyphase filter; 8-channel IDFT-Polyphase; and 8-channel Polyphase-DFT. Simulation results for the 32-point DFT circuit configuration show a performance of 240MOPS. Simulation results for the 8-channel Polyphase filter and 8-channel IDFT-Polyphase/Polyphase-DFT circuit configurations show that a throughput of 120 and 60MSPS respectively can be achieved. The circuit is scalable and can be extended to accommodate larger configurations and architectures. The scalability and reconfigurability of the circuit's architecture provides a flexible solution for multi-carrier wireless applications incorporating Polyphase-DFT circuits.

Additional Metadata
Persistent URL dx.doi.org/10.1109/MWSCAS.2008.4616886
Conference 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Citation
Ho, H., Szwarc, V., & Kwasniewski, T. (2008). A reconfigurable systolic array SoC design for multicarrier wireless applications. Presented at the 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS. doi:10.1109/MWSCAS.2008.4616886