Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies
Power consumption of integrated circuits has been rapidly increasing over the past decades, and this is expected to continue for the foreseeable future, resulting in shorter battery life and excessive heat generation. Therefore, it is essential to develop techniques for low power design while maintaining high performance. This paper presents solutions to these problems by combining asynchronous design with multi-threshold CMOS technology to maintain high performance while reducing power consumption. Multi-Threshold C-Element circuits are proposed, and these are used to implement multi-threshold micropipeline circuits. A multi-threshold implementation of the GasP pipeline is also proposed. Two application circuits are designed to the custom layout level using a 130nm multi-threshold CMOS process technology. The proposed multithreshold micropipelines were found to reduce dynamic current by up to 34%, static leakage current by up to 91% and delay by up to 38% compared to single threshold implementations. The mutli-threshold GasP pipelines achieved up to 24% reduction in dynamic current, 21% reduction in static leakage current and 37% reduction in delay. Copyright 2008 ACM.
|Keywords||Asynchronous, C-element, Gasp, Low power, Multi-threshold, Pipeline|
|Conference||GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008|
Shreih, R. (Raghid), & Shams, M. (2008). Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies. Presented at the GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008. doi:10.1145/1366110.1366157