A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.10 μm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.

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Conference 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Citation
Li, M. (Miao), Kwasniewski, T, Wang, S. (Shoujun), & Tao, Y. (Yuming). (2005). A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology. Presented at the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005.