In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for this class of simulations to be performed efficiently. The proposed method exploits the recently developed algorithm using transverse partitioning and waveform relaxation. A new partitioning algorithm is also proposed to create additional parallelism during transient simulations. In this approach, for a simulation of m lines run on p processors, the computational complexity is 0(mp-1). This provides considerable savings as opposed to O(m β),3 ≤ ,β ≤ 4 for full coupled-line simulations.
17th Conference on Electrical Performance of Electronic Packaging, EPEP 2008
Department of Electronics

Paul, D., Nakhla, N.M., Achar, R, & Nakhla, M.S. (2008). Parallel algorithm for analysis of high-speed interconnects. In Electrical Performance of Electronic Packaging, EPEP (pp. 191–194). doi:10.1109/EPEP.2008.4675911