Decision feedback equalization for high-speed backplane data communications
The proposed 2 post-tap decision feedback equalizer (DFE) implementation consists of two equalizing amplifiers (summing nodes) connected to incoming data and feedback loops. Two parallel branches consisting of equalizing amplifier and two flip-flops each are also present and followed by a MUX. The design is verified by HSPICE using 0.18 μm CMOS process parameters. Simulation results show an increase of horizontal and vertical eye opening at data rates up to 8Gbps. Data is transmitted over a 34" FR4 backplane with BER less than 10-15. The total power consumption is 12mW at a 1.8V supply.
|Conference||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005|
Chen, J. (Jing), Li, M. (Miao), & Kwasniewski, T. (2005). Decision feedback equalization for high-speed backplane data communications. Presented at the IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005. doi:10.1109/ISCAS.2005.1464827