Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology

Wang, B. (Bo), Chen, D. (Dianyong), Liang, B. (Bangli) and T. Kwasniewski (Tad)

2008-12-01

Presented at the 1st Microsystems and Nanoelectronics Research Conference, MNRC 2008 (October 2008)

Additional Metadata
Keywords	CML, CMOS, Deep-submicron (DSM), High-speed digital circuits, Nano-technology, Ultra-deep-submicron (UDSM)
Persistent URL	dx.doi.org/10.1109/MNRC.2008.4683408
Conference	1st Microsystems and Nanoelectronics Research Conference, MNRC 2008
Organisation	Department of Electronics
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Wang, B. (Bo), Chen, D. (Dianyong), Liang, B. (Bangli), & Kwasniewski, T. (2008). Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology. Presented at the 1st Microsystems and Nanoelectronics Research Conference, MNRC 2008. doi:10.1109/MNRC.2008.4683408

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