2008-12-01
Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology
Publication
Publication
Presented at the
1st Microsystems and Nanoelectronics Research Conference, MNRC 2008 (October 2008)
| Additional Metadata | |
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| Keywords | CML, CMOS, Deep-submicron (DSM), High-speed digital circuits, Nano-technology, Ultra-deep-submicron (UDSM) |
| Persistent URL | dx.doi.org/10.1109/MNRC.2008.4683408 |
| Conference | 1st Microsystems and Nanoelectronics Research Conference, MNRC 2008 |
| Citation |
Wang, B. (Bo), Chen, D. (Dianyong), Liang, B. (Bangli), & Kwasniewski, T. (2008). Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology. Presented at the 1st Microsystems and Nanoelectronics Research Conference, MNRC 2008. doi:10.1109/MNRC.2008.4683408
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