Signal integrity analysis is becoming extremely important in validation of high-speed designs. In a system containing highspeed interconnects, the presence of a large number of coupled lines presents difficult challenges for performing fast simulations. In this paper, a novel parallel algorithm based on both physical and time-domain partitioning is proposed that allows for the efficient analysis of circuits containing large number of coupled lines. The proposed method exploits the recently developed method of combining transverse partitioning and wavefonn relaxation. Examples are provided to demonstrate the efficiency and scalability of the proposed algorithm.

Additional Metadata
Persistent URL dx.doi.org/10.1109/EDAPS.2008.4736035
Conference 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008
Citation
Paul, D., Nakhla, N.M., Achar, R, & Nakhla, M.S. (2008). Coupled high-speed interconnect analysis on parallel platforms. In 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings (pp. 202–205). doi:10.1109/EDAPS.2008.4736035